1. Field of the Invention
The present invention relates to a method of forming a dual damascene copper (Cu) wire, and more particularly, to a method of forming a dual damascene copper wire having superior Cu gap-filling ability and an enlarged process window.
2. Description of the Prior Art
A dual damascene process is a method of forming a conductive wire coupled with a via plug in a dielectric layer. The dual damascene structure, comprising a trench and a via hole, is used to connect devices and wires in a semiconductor wafer within various layers and is isolated from other devices by the inter-layer dielectrics (ILD) around it. Since the resistivity of copper is smaller than the resistivity of aluminum (Al), a large current can be sustained in a small area. Consequently, chips having high speed, high integration, and high efficiency (with 30-40% improvement) are fabricated. To fill copper into the dual damascene structures thus becomes a trend in fabricating dual damascene copper wires. As integrated circuit technology advances, improving the yield of the dual damascene structure, simplifying the process flow and reducing the production cost are important issues in the manufacturing process of integrated circuits at the present time.
Please refer to FIG. 1 to FIG. 7. FIG. 1 to FIG. 7 are schematic diagrams of a method of fabricating a dual damascene copper wire according to the prior art. As shown in FIG. 1, a semiconductor wafer 10 comprises a substrate 12, a conducting layer 14 disposed on a predetermined region of a surface of the substrate 12, and a passivation layer 16 composed of silicon nitride disposed on a surface of the conducting layer 14. Since the other elements disposed on the surface of the substrate 12 are not the concerning parts in the dual damascene process, they are not shown in FIG. 1 and in other figures. Furthermore, the semiconductor wafer 10 comprises a low-k layer 18, a passivation layer 20, a low-k layer 22, and a hard mask layer 24 sequentially disposed on a surface of the passivation layer 16.
The low-k layers 18 and 22 are normally formed of spin-on-coating (SOC) low-k materials, such as HSQ or FLARE™. Since many of the low-k materials (especially the organic low-k materials) are fragile, denser materials, such as silicon nitride, are chosen to form the passivation layer 20 on the low-k layer 18 to harden the low-k layer 18. Similarly, another passivation layer is required to cover the low-k layer 22. The hard mask layer 24 covering the low-k layer 22 functions not only as the passivation layer but also as a hard mask in subsequent etching processes. The hard mask layer 24 is composed of silicon nitride or silicon oxy-nitride.
As shown in FIG. 2, after the stacked structure shown in FIG. 1 is formed, a photolithographic and etching process is performed to form an opening 25 in the hard mask layer 24 until reaching a top surface of the low-k layer 22. The opening 25 defines a pattern for forming a trench of the dual damascene structure. Following this, as shown in FIG. 3, a photo resist layer 26 is coated on the surface of the semiconductor wafer 10. Another photolithographic process is performed to form an opening 27 penetrating through the photo resist layer 26 down to the top surface of the low-k layer 22. The opening 27 functions to define a pattern for forming a via hole of the dual damascene structure, so a width of the opening 27 must be smaller than that of the opening 25. In addition, the opening 27 is disposed inside the opening 25, such that a self-aligned contact (SAC) etching process is used thereafter to form the dual damascene structure.
As shown in FIG. 4, a first etching process, such as an anisotropic dry etching process, is performed along the opening 27 to remove portions of the low-k layer 22 and the passivation layer 20 not covered by the photo resist layer 26, forming an opening 28 until reaching a top surface of the low-k layer 18. Thereafter, a resist stripping process is performed to completely remove the photo resist layer 26.
As shown in FIG. 5, a second etching process is performed by utilizing the passivation layers 20 and 16 as stop layers to simultaneously remove portions of the low-k layers 22 and 18 not covered by the hard mask layer 24. Following this, both the passivation layer 20 and the passivation layer 16 not covered by the hard mask layer 24 are removed. As a result, a trench 30 penetrating through the low-k layer 22 and the passivation layer 20, and a via hole 31 penetrating through the low-k layer 18 and the passivation layer 16 down to a top surface of the conducting layer 14 are simultaneously formed.
As shown in FIG. 6, a deposition process is then performed to form a barrier layer 32 on the semiconductor wafer 10. The barrier layer 32 is formed of silicon nitride to prevent diffusion of copper or tungsten from various conductive layers into silicon. Alternatively, the barrier layer 32 can also be composed of composite materials such as silicon nitride/Ta/Ti/TiN to increase adhesion between the dual damascene structure and a metal layer covering the dual damascene structure. Following that, a re-sputtering process is performed to remove portions of the barrier layer 32 to expose the top surface of the conducting layer 14. A physical vapor deposition (PVD) process is thereafter performed to form a Cu seed layer 34 on the surface of the semiconductor wafer 10. The Cu seed layer 34 covers the exposed conducting layer 14 and the barrier layer 32. The objective for forming the Cu seed layer 34 is not only to provide a conductive path, but is also to provide a nucleation layer to allow the electric plating copper to nucleate and grow on it later. After that, an electric copper plating (ECP) process is performed to form a metal layer 36 on a surface of the Cu seed layer 34 to fill up both the trench 30 and the via hole 31.
As shown in FIG. 7, a chemical mechanical polishing process is performed by utilizing the barrier layer 32 as an end-point to remove the metal layer 36 and the Cu seed layer 34 disposed outside the trench 30 and the via hole 31, such that the remaining metal layer 36 inside the trench 30 and the via hole 31 is aligned with the surface of the barrier layer 32 disposed outside the trench 30. Finally, a passivation layer 38, such as a silicon nitride layer, is formed on the surface of the semiconductor wafer 10 to complete the fabrication of the dual damascene copper wire.
With regarding to the physical characteristics of the low-k material and the low resistivity cupper wire, these two materials go together perfectly to effectively improve the RC delay caused by signal transmission between wires when the device size is shrunk. However, such a perfect combination faces a bottleneck. Since the Cu seed layer 34 is formed by a physical vapor deposition process, and the thin film formed by the physical vapor deposition process is characterized in poor step coverage, an overhang phenomenon thus occurs to result in a discontinuous and not uniform Cu seed layer 34. As a result, voids are produced in the metal layer 36 when the metal layer 36 is filled into the dual damascene structure subsequently, leading to the poor Cu gap-filling problem. Due to the poor adhesion force between the Cu seed layer 34 and the barrier layer 32, peeling phenomenon occurs in the metal layer 36 during the subsequent chemical mechanical polishing process to decrease the yield of the dual damascene copper wire greatly. Please refer to FIG. 8. FIG. 8 is a schematic diagram illustrating defects produced in a dual damascene copper wire according to the prior art. As shown in FIG. 8, the overhang phenomenon of the Cu seed layer 42 tends to occur at an open of the via hole 44, and the discontinuous phenomenon of the Cu seed layer 42 tends to occur at a bottom of the via hole 44. Therefore, the Cu seed layer 42 at the lower layer and the bottom layer grows slowly such that the bottom up filling behavior is not able to dominate the filling mechanism during the electric copper plating process. As a result, voids 48 are produced in the metal layer 46 after the electric copper plating process.
Therefore, it is very important to develop a new method of forming a dual damascene copper wire to fill in the copper conductive layer into the dual damascene structure, having a small line width and a high aspect ratio, successfully without increasing the complexity of processing. In addition, this method should form the dual damascene copper wire having a low resistivity, a low surface roughness, and a superior adhesion.